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Using FPGA to optimize radar and advanced sensors


in modern urban and coastal warfare, it is very important to master the battlefield environment in advance. Soldiers in the air, at sea and on land need to understand the surrounding environment and find out the enemy situation as soon as possible

the current military sensors have a great demand for environmental data acquisition and processing. In order to process data as soon as possible and provide soldiers with "actionable intelligence" information, sensor system logic needs to optimize and combine various logic and digital signal processing (DSP) functions, adopt high-speed transceiver, improve the flexibility of design in power consumption and performance, and provide very reliable design process to meet the needs of end users

as shown in Figure 1, the radar system can be used on a variety of platforms, including military and non military systems. Many of these systems use array and projection array technology. These systems have higher and higher requirements for digital logic, requiring smaller components and circuit boards

figure 1 Radar application

for designers who pay attention to the military advanced sensor market, Altera has strong advantages in simple and reliable tool flow, intellectual property (IP) library and high-efficiency logic devices

fusion of military electronic systems

military systems and vehicles are generally equipped with a large number of discrete electronic subsystems. Among them, the most complex are directional radar, surveillance radar, electronic warfare and anti countermeasure, imaging, and radio communication equipment. As shown in Figure 2, in many military systems, multi-mode active electronic scanning array (AESA) technology is adopted, and these functions gradually appear the trend of integration. The demand of the system for digital logic and state logic has increased significantly, requiring the industry to provide more mature and reliable programmable logic devices (PLDs)

figure 2 Integration of electronic functions in military systems

various military tasks have obvious functional overlap in the market (Figure 3). The significant improvement of memory and semiconductor performance makes it possible to accomplish these tasks in multi role systems. Altera FPGA and structured ASIC provide powerful and easy-to-use software. The company also cooperates reliably with logic design software partners. Therefore, it plays an important role in the development trend of this technology. A large number of IP module libraries simplify such complex military designs

figure 3 The overlap of military electronic market

other technologies affect

the rapid development of active arrays in sensors is the main technical force to promote logic devices. A large number of array cells mean more design work, more complex bunching algorithms, more intensive integration and testing, and longer system logistics supply lines

in order to meet various computing needs of military systems, government customers have increased their investment in configurable processors and completed front-end and back-end processing functions at the same time. Although some technologies have been commercialized, programmable logic is the best intermediate design step to complete key sensor projects

the sensor design adopts multiple input multiple output (MIMO) sensor array for test (as shown in Figure 4). The receiver in MIMO system completes the phase delay correlation calculation between multiple orthogonal transmission waveforms, making full use of the improvement of electronic device density and computing capacity. Developers who want to stand out in this market should use these most advanced high-density devices to complete the design with the most concise design process and the most effective compilation means

figure 4 MIMO sensor

makes AESA more flexible

aesa is a very powerful technology, which can establish a highly adaptive adjustment beam, track multiple targets or focus on the electromagnetic energy at one position. In order to make full use of the control function of the system, the designers try their best to realize the signal processing function in the transmitting and radiating unit of the system. This includes waveform creation and compression, bunching, correlation and preprocessing. Most of the functions are completed in the optimized parallel FPGA logic, which accelerates the bunching algorithm and waveform adaptive function, and shortens the system response time

high density Stratix series FPGA is the best tool to optimize the performance of radar system. The increase of logic density makes it possible to realize more functions in one chip. The improved DSP unit simplifies the arithmetic implementation of the matrix and improves the flexibility. The very flexible 18x18 bit multiplier can be divided into 9x9 bit units, or the 54 bit multiplier with high success efficiency and logic efficiency can be combined to complete floating-point operations. Altera's floating-point operators have been tested and are suitable for a variety of high-performance applications

advanced sensor requirements

compared with other engineering fields, the challenges faced by military advanced sensor design are very unique. It includes all design constraints in the commercial market, as well as design consistency across two to three generations of component technologies, strict testing and verification, as well as updating the design and realizing the product life cycle. Some examples of these constraints are:

· high serial data stream capacity: digital antenna technology turns to analog-to-digital fusion and is closer to the receiver. It is necessary to improve the signal resolution to complete digital filtering

· complex mathematical operation: signal preprocessing and matrix operation require a large number of DSP module units to ensure the tasks previously completed by the digital signal processor

· sensitive to heat dissipation: generally, the sensor system has a long service time and needs heat dissipation during continuous operation

· logic density of multi role electronic system: since many military tasks are completed by the same array, the requirements for sending and receiving electronic systems are very high

· speed and delay performance: the speed level and delay of logic devices in the sensor array and all interface delays between logic devices will affect the response time and the performance of the bunching algorithm

· component supply: the sensor system is very complex, and failure to supply a component as planned will have serious consequences for other parts of the system

· ease of use of tool process: millions of logic units (LES) are integrated into a system design, and the design, compilation and testing of a large number of logic codes may push up the cost and affect the progress

· signal integrity: more and more receiver data are related to each other in the final processing process, and a small signal error will also have a great impact on the sensor algorithm. Therefore, the signal integrity of digital components is very important

high speed serial i/o

the military sensor system uses various high-speed serial interfaces (see Table 1) to process a large amount of data generated by the transmitting/receiving unit. Altera provides internal solutions as well as partner solutions for most protocols, as well as a dedicated seriallite II standard that reduces overhead and latency. Table 1 Altera and its partners' standard and high-speed interface protocols support a variety of features of the seriallite II protocol developed by Altera internally, which are very suitable for military sensor design. These features include:

· 1 to 16 times the rate, the maximum 6.375 gbps

· very low latency and efficient Le implementation

· support one-way rate and half duplex throughput, and are suitable for one-way sensor flow

high speed sensor data stream products, such as Curtis Wright controls fibrextreme serial FPDP (ansi/vita 17.) The data link adopts Altera FPGA to realize very reliable serial interface, with mature signal integrity and high data rate

power consumption and heat dissipation advantages

military users require the use of components with good heat dissipation performance in the sensor array to improve flexibility and accuracy, and will not increase the system volume or weight due to the improvement of sensor performance. This means more compact sensor electronics, complex power consumption and heat dissipation requirements

system designers have never been able to directly control the power consumption and heat dissipation of programmable logic devices. The Altera design process has five advantages to help achieve the best balance between system power consumption and performance. Altera's patented programmable power technology enables designers to increase power on key logic paths that need to improve performance, and reduce power where it is not needed. Designers can choose between 0.9V and 1.1V FPGA core voltage to balance power consumption and performance. In addition, the powerful Altera quartz II design system also has two new features: dynamically and intelligently turn off unused power connections and optimize power wiring

as shown in Figure 5, FPGA designers have flexible design margin to adjust, while meeting the power consumption and performance requirements. The new hull will not only reduce the resources consumed by shipbuilding

figure 5 Five methods that military designers can adopt to optimize design power consumption and performance

at the 65 nm FPGA technology node (the specific use methods IX III and Virtex-5 of the strat abrasion tester), Figure 6 shows the unit equivalent Le power consumption curve. Stratix series FPGAs have better performance at high performance points. According to system requirements, they can even further reduce power consumption. For the design with 1.1V core voltage, the power consumption can be reduced by 23%, while for the design with 0.9V core voltage, the power consumption can be reduced by 40%

figure 6 Typical power consumption curve of Stratix and virtex series FPGAs

FPGA is used for system prototype development - zero risk transition to ASIC

another method to reduce the power consumption of sensor system is to convert the digital logic in the system from Stratix series FPGAs to hardcopy structured ASIC (Figure 7). At the prototype design stage, it can be decided to switch to ASIC without prior engineering planning or investment. This conversion can be used for product improvement, or it can be part of engineering improvement suggestions or product suggestions

figure 7 Quartus II software enables designers to quickly convert from FPGA to structured asic

as shown in Table 2, the dynamic and static power consumption of designers in their programmable logic are reduced by 50% and 90% respectively. This can be achieved at the minimum chip cost (NRE) - about 20% of the ASIC design cost, and there is basically no schedule or technical risk. After reducing the power consumption, the sensor system can further improve the performance of the original product, and continuously improve the scanning algorithm and tactical performance. Table 2 Seamlessly migrate to the solution with the lowest power consumption

when using Altera FPGA and Quartus II software for design, the flexibility and programmability of FPGA can always be realized at the same time, and the heat dissipation of programmable logic can be greatly reduced through structured ASIC. This is a very favorable design choice in meeting the strict system power consumption and heat dissipation requirements of military sensors

component supply

military system development with complex sensors is one of the most difficult projects to manage. The project integrates a large number of technologies, some of which have not even been tested in the initial prototype

altera always delivers all FPGA devices on time or even in advance (see Figure 8). The latest generation of low-power cyclone III and flexible high-density Stratix III FPGAs are also delivered to early users without defects on schedule. D=h plus 0-h unloading 0 using Altera PLD in radar and advanced sensor system, the project manager can greatly reduce the technical and schedule risks and concentrate on solving the most difficult technical problems

figure 8 Altera's product release history, all products are delivered 100% on time

simplified design process

the design complexity of radar and advanced sensor systems increases almost exponentially. Designers need design tools that can shorten compilation time, control design risks, and shorten testing and verification time. Moreover, such tools also have powerful DSP design capabilities

use Altera Designer

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